Non-volatile memory system having internal data verification test mode

ABSTRACT

A memory system including means for verifying the contents of a memory cell contained in a memory array to determine if a shift in the threshold voltage level has occurred. The memory system is placed into a test mode of operation in which an internal program or erase verify operation is executed under the control of the system&#39;s internal state machine. Once in the mode, the memory system steps through each memory cell, address by address, and reads the contents of the cell using the appropriate reference voltage for a programming or erase operation. A status register bit is set indicating successful completion of the verification operation for a block of memory cells. A register bit is also set if a cell fails the verification operation. This provides a more accurate determination of the state of a memory cell than can be achieved by performing an external read operation using read operation or data verification reference voltage levels.

TECHNICAL FIELD

The present invention relates to non-volatile memory systems, and morespecifically, to a memory system having a test mode of operation inwhich the data contained in the memory cells can be verified using theinternal data verification process which is part of a programming orerase operation. This provides a test engineer with more reliable statusinformation regarding the data contained in the memory cells then thatobtained by performing a read operation or using external verificationmethods.

BACKGROUND OF THE INVENTION

In early integrated circuit memory systems, the detailed operation ofthe memory system was controlled directly by a processor unit whichutilized the memory. This was referred to as external control of thememory system operations because the control means was external to thememory itself. Since the operation of many memory systems requires asubstantial amount of processor overhead, and since differentmanufacturers require different operations for optimizing theirparticular memories, many such systems now include an internal statemachine (ISM) for controlling the operation of the memory system. Theinternal state machine controls the execution of the primary operationsof the memory system, including reading, programming and erasing of thememory cells. Each of these primary operations is comprised of a largenumber of sub-operations which are necessary to carry out the primaryoperations, with these sub-operations also being controlled by the statemachine.

FIG. 1 is a functional block diagram of a conventional non-volatilememory system 1. The core of memory system 1 is an array 12 of memorycells. The individual cells in array 12 (not shown) are arranged in rowsand columns, with there being, for example, a total of 256K eight bitwords stored in array 12. The individual memory cells are accessed byusing an eighteen bit address A0-A17, which is input by means of addresspins 13. Nine of the eighteen address bits are used by X decoder 14 toselect the row of array 12 in which a desired memory cell is located andthe remaining nine bits are used by Y decoder 16 to select the column ofarray 12 in which the desired cell is located. Sense amplifiers 50 areused to read the data contained in a memory cell during a read operationor during a data verification step in which the state of a cell isdetermined after a programming, pre-programming, or erase operation. Thesense amplifier circuitry can be combined with the data compare andverify circuits used to compare the state of a cell to a desired stateor to the input data used in programming the cell.

Programming or erasing of the memory cells in array 12 is carried out byapplying the appropriate voltages to the source, drain, and control gateof a cell for an appropriate time period. This causes electrons totunnel or be injected from a channel region to a floating gate. Theamount of charge residing on the floating gate determines the voltagerequired on the control gate in order to cause the device to conductcurrent between the source and drain regions. This is termed thethreshold voltage, V_(th), of the cell. Conduction represents an “on” orerased state of the device and corresponds to a logic value of one. An“off” or programmed state is one in which current is not conductedbetween the source and drain regions and corresponds to a logic value ofzero. By setting the threshold voltage of the cell to an appropriatevalue, the cell can be made to either conduct or not conduct current fora given set of applied voltages. Thus, by determining whether a cellconducts current at a given set of applied voltages, the sate of thecell (programmed or erased) can be found.

Memory system 1 contains internal state machine (ISM) 20 which controlsthe data processing operations and sub-operations performed on memoryarray 12. These include the steps necessary for carrying outprogramming, reading and erasing operations on the memory cells of array12. In addition, internal state machine 20 controls such operations asreading or clearing status register 26, identifying memory system 1 inresponse to an identification command, and suspending an eraseoperation. State machine 20 functions to reduce the overhead required ofan external processor (not depicted) typically used in association withmemory system 1.

For example, if memory cell array 12 is to be erased (typically, all orlarge blocks of cells are erased at the same time), the externalprocessor causes the output enable pin {overscore (OE)} to be inactive(high), and the chip enable {overscore (CE)} and write enable {overscore(WE)} pins to be active (low). The processor then issues an 8 bitcommand 20H (0010 0000) on data I/O pins 15 (DQ0-DQ7), typically calledan Erase Setup command. This is followed by the issuance of a secondeight bit command DOH (1101 0000), typically called an Erase Confirmcommand. Two separate commands are used to initiate the erase operationin order to minimize the possibility of inadvertently beginning an eraseprocedure.

The commands issued on I/O pins 15 are transferred to data input buffer22 and then to command execution logic unit 24. Command execution logicunit 24 receives and interprets the commands used to instruct statemachine 20 to initiate and control the steps required for erasing array12 or carrying out another desired operation. If a programming operationis being executed, the data to be programmed into the memory cells isinput using I/O pins 15, transferred to input buffer 22, and then placedin input data latch 30. The data in latch 30 is then made available tosense amplifier circuitry 50 for the programming and data verificationoperations. Once a desired operation sequence is completed, statemachine 20 updates 8 bit status register 26. The contents of statusregister 26 is transferred to data output buffer 28, which makes thecontents available on data I/O pins 15 of memory system 1. Statusregister 26 permits the external processor to monitor certain aspects ofthe status of state machine 20 during memory array write and eraseoperations. The external processor periodically polls data I/O pins 15to read the contents of status register 26 in order to determine whetheran erase sequence (or other operation) has been completed and whetherthe operation was successful.

Memory system 1 verifies the status of the memory cells after performingprograming or erasing operations on the cells. Verification occurs byaccessing each memory element and evaluating the margins (the voltagedifferential between the threshold voltage of the memory cells andground level) that the element has after the operation. The system thendecides whether the element needs to be reprogrammed or erased furtherto achieve a desired operational margin.

The memory array needs to be programmed first in a pre-programming cyclebefore it can be erased. This is to avoid over-erasing the bits in somememory elements to a negative threshold voltage, thereby rendering thememory inoperative. During this cycle of pre-programming, the memorysystem needs to check to see if the bits are programmed to a sufficientthreshold voltage level. This is accomplished by a pre-programmingverification cycle that uses a different evaluation procedure than aregular read operation would use. After successful completion of thepre-programming cycle, a high voltage erase operation is executed. Afterthe erase operation is completed, some memory systems go through anoperation to tighten the distribution (reduce the variance) of memoryelement threshold voltages. This makes the manufacturing process easierand more reproducible. After this procedure, the memory system mayperform a re-verify operation to determine if the data in the memoryarray has remained undisturbed.

FIG. 2 is a state diagram showing the process flow (sub-operations) of amemory system of the type shown in FIG. 1 during the pre-programming,high voltage erase, and distribution adjustment cycles of a completeerase operation. The complete erase operation starts with a pre-programcycle 200. This sub-operation programs all the elements in the memoryarray to a logic zero value to make sure that the erase process startsfrom a known cell threshold voltage level. This part of the completeerase operation is used to reduce the possibility of over erasure ofsome of the memory elements during the later steps of the operation.

The pre-program cycle begins with an operation which increments theaddress of the memory cell which is to be pre-programmed 202. This isdone because the pre-programming operation is executed on a cell by cellbasis. This step is followed by a high voltage level set-up stage 204which prepares the system for application of the high voltage levels(typically about 12 volts is applied to the gate of each memory cell and5 volts to the drain) used for programming or erasing a cell. The highvoltage level used for writing to (programming) the cell is then appliedin stage 206.

The appropriate voltage levels for executing the data verificationsequence (reading the data programmed in the cell and comparing it to adesired value) are applied to the appropriate circuitry at stage 208.This is followed by a program verification stage 210 which verifies thatthe programmed cell has a sufficient threshold voltage margin. This istypically accomplished by comparing the threshold voltage of the cell toa reference cell having a desired threshold voltage (corresponding to alogic value of 0). If the verification operation was not successful,steps 204, 206, 208, and 210 are repeated. Once the verification stagefor a particular memory cell is successfully completed, it is followedby a program clean up stage 212.

Program clean up stage 212 conditions all internal nodes of the memoryarray to default values in order to prepare the memory system for thenext operation. This concludes the pre-programming cycle for a givenmemory cell. The address of the cell to be operated on is thenincremented at stage 202 and the process repeats itself until the lastcell in a memory block to be erased is pre-programmed. At this time, theincremented address will point to the first address location in theblock, which is the first address for the next operation. When thisoccurs, all of the memory cells have been successfully pre-programmedand control is passed to the high voltage erase cycle 220.

In the high voltage erase cycle, the memory system performs a blockerase operation on all of the cells contained in a block of memory. Thefirst stage in the cycle is a high voltage level set-up stage 222 whichprepares the memory block for application of the high voltage pulse(es)used for erasing the cells. This is followed by a high voltage stage 224in which a short duration, high voltage pulse is applied to erase all ofthe memory cells in the block of cells. This is followed by a set-upverify stage 226 which applies the appropriate voltage levels for thedata verification stage to the corresponding circuits. The next stage isan erase verify stage 228 which verifies that the erase operation wassuccessfully carried out on each cell in the block. This is accomplishedby accessing the cells, address by address, and comparing the thresholdvoltage of the cell to a reference cell having a desired thresholdvoltage level (corresponding to a logic value of 1).

If the erase operation was not successfully carried out (a cell was noterased to the threshold voltage margin corresponding to the desiredlogic value), control is passed back to the high voltage level set-upstage 222 and the high voltage cycle is carried out again to erase theentire block of cells. If the erase operation was successful for thecell under consideration, the address of the memory cell is incremented230 and the next cell is tested for verification of the erase operation.Thus, if the maximum address of the cells in the block of memory has notbeen reached, erase verify stage 228 is carried out on the next memorycell in the block. If the maximum address for cells in the block hasbeen reached (meaning that all the cells in the memory block have beensuccessfully erased), control is passed to the distribution adjustmentcycle 240.

The distribution adjustment sub-operation is used to tighten thedistribution (reduce the variance) of the threshold voltages of theerased memory elements. This is done by applying high voltages (i.e. 12volts) to the gates of all the memory cells in the memory block, withthe memory cell drains floating and the sources at ground potential.

The distribution adjustment cycle begins with a high voltage set-upstage 242, which is followed by a high voltage stage 244 in which thevoltages used to perform the adjustment sub-operation are applied. Thisis followed by set-up verification 246 stage which applies theappropriate voltage levels to the corresponding circuits, and eraseverification 248 stage which acts to insure that all of the erased cellsare still in an erased state. If the erase verification procedure fails,a final erase 249 stage may be executed. In the final erase stage, ashort erase pulse is applied to the cells in the block. After completionof the previous steps, the memory elements are checked to determine ifthey still contain the appropriate data. At this point the eraseoperation is completed.

A programming operation is carried out by following a set of stepssimilar to those followed in pre-program cycle 200 of FIG. 2. Inparticular, stages 204 through 212 of FIG. 2 describe the primaryfunctions carried out in a regular programming operation. As a programoperation is typically carried out on a specific memory cell, theincrement address state 202 used in the pre-program cycle to facilitatepre-programming of every cell in the memory array is not accessed.Another difference between the programing and pre-programming operationsis that in a programming operation, program verify state 210 is designedto read the programmed data and compare it to data obtained from inputdata latch 30, rather than to a logic value of zero, as in thepre-programming operation.

As noted, in both the pre-programming and high voltage erase cycles of acomplete erase operation, and in a programming operation, the state of amemory cell is verified to determine if the operation was successfullyexecuted. This is accomplished by an internal data verification stagewhich is performed under the control of the internal state machine. If amemory cell does not pass the verification stage, the pre-programming,programming, or high voltage erase stage is repeated until the cellsuccessfully passes the verification procedure, or until the highvoltage pulse counter reaches its maximum value. At this point theoperation is terminated and a status bit (contained in status register26) is set indicating a problem with the block of memory cells.

There are some situations in which a test engineer is interested inknowing the status of a memory cell which has previously been programmedor erased. For instance, memory systems of the type shown in FIG. 1 areoften manufactured well in advance of their sale and/or usage in otherdevices. In order to check whether the memory cells have maintainedtheir previously set threshold voltage after an extended period of time,it is useful to conduct a data verification operation on the cells. Suchan operation can also be used to determine the rate at which electronsare leaking from the floating gate by performing a data verificationoperation with a variable reference voltage. A test engineer may also beinterested in knowing the status of a memory cell or block of cellsafter execution of a pre-programming, programming, or erase cycle butwithout having the memory system repeat the cycle until it issuccessful. This allows an examination of the effect of the high voltagepulses used in the programming and erase operations on the thresholdvoltages of the memory cells.

One means of determining the status of a memory cell in such instancesis to perform a read operation on the cells. The sense amplifieremployed in normal reading as well as data verification operations(e.g., sense amplifier 50 of FIG. 1) is typically a differentialamplifier having two input signals: a signal from the selected cellindicative of the cell's threshold voltage, V_(th), and a referencesignal corresponding to a reference threshold voltage, V_(ref). In anormal read operation, reference voltage V_(ref) is typically 4 volts,and the measured threshold voltage V_(th) is typically 3 volts or 5.5volts, depending on whether the cell stores a “1” or a “0” bit. Thus,the sense amplifier operates with a substantial noise margin during anormal read operation because there is a significant voltage rangebetween V_(ref) and the programmed or erased threshold voltage of acell. The use of such a noise margin allows an accurate determination ofwhether the memory cell is programmed or erased. However, it provideslittle information regarding small, but potentially important changes inthe threshold voltage of the cell caused by electrons leaking from thefloating gate of the cell.

One method for performing an externally controlled verificationprocedure is described in U.S. Patent Application Ser. No. 08/511,614,filed Aug. 4, 1995, entitled “Memory Circuit for Performing ThresholdVoltage Tests on Cells of a Memory Array”, the contents of which ishereby incorporated in full by reference. In the above-identified patentapplication, a test mode of operation is described in which a dataverification operation is performed on a memory cell by executing a readoperation on the cell using a program or erase verification value forthe reference voltage instead of the normal read operation value.Although this has the benefit of setting the reference voltage level atvalues which provide a more accurate assessment of the state of thememory cell, the method does have a disadvantage. This disadvantage willbe explained with reference to FIG. 3, which is a block diagram of aprior art data input/output circuit 300 for programming memory cells ofa non-volatile memory array, and for reading data indicative of thestate of those cells.

As shown in FIG. 3, an input/output pad 302 is connected to circuitelements which form a data read path 304 and a data write path 306 to amemory array (not shown). Pad 302 is part of the metallization of theintegrated circuit containing the memory array and is connected by meansof a wire bond to a data pin of the integrated circuit package. There isone data input/output circuit 300 associated with each data input/outputline of the memory, with there typically being eight or sixteen datainput/output lines depending upon the memory architecture.

Read path 304 and write path 306 are electrically connected to data line308, which connects those paths to the memory array by means of decodingmultiplexer 310. Decoding multiplexer 310 functions to connect read path304 and write path 306 to a selected one of the plurality of bit linesof the array, where one of the bit lines is represented by line 312. Theselected bit line, which is determined by an address provided to thememory, is connected to the drain of the memory cell being read orprogrammed.

Write path 306 includes a data latch 314 for storing data input by meansof pad 302. Latch 314 is activated or enabled by latch enable signal315. The latched data is sent to data input buffer or driver 316, whichproduces the voltage on line 318 which is applied to the bit line of thecell to be programmed. Input buffer 316 is typically implemented in theform of a tri-statable driver having an output which can be placed in ahigh impedance mode and effectively disabled during a read operation.The disabling of input buffer 316 is achieved by means of tri-statecontrol line 317.

As noted, decoding multiplexer 310 is used to access a desired memorycell in the array for purpose of reading data from or writing data tothat cell. When reading a memory cell of the array, multiplexer 310 isused to access the bit line connected to the selected memory cell in thearray. In the event the cell being read is in an erased state, the cellwill conduct a current which is converted to a voltage on line 308.Sense amplifier 320 determines the state of the cell, i.e., whether itis programmed or erased (corresponding to a binary value of 0 or 1,respectively). This determination is based on comparing the voltage onlines 308 and 312 to a reference voltage. The outcome of this comparisonbetween the two input voltages is an output which is either high or low,corresponding to a digital value of one or zero. The output of senseamplifier 320 is sent to output buffer 322 which drives the data tooutput pad 302 where it is accessed by a user.

During a normal read operation in which the reference voltage isapproximately 4 volts (so that a wide noise margin is present), thelarge differential between the inputs to the sense amplifier results ina stable, unambiguous output. This is because noise in the circuit isgenerally insufficient in magnitude to produce a false positive in theoutput of the sense amplifier. As a result, the output is stable and theoutput buffer only generates an output in response to a single change inthe sense amplifier signal.

However, when conducting a read operation using the reference voltagelevels typically used for a data verification operation, the inputs tothe sense amplifier have a much smaller differential. During an internaldata verification stage of the type shown in FIG. 2 (i.e., stage 210 or228), the reference voltage (V_(ref)) for a programming operationverification is typically set at 5.5 volts, and an adequately programmedcell has a measured threshold voltage (V_(th)) greater than 5.5 volts.Since the two inputs of the sense amplifier are much closer to eachother in this case than for a regular read operation, the senseamplifier's output is more susceptible to error due to noise and thesense amplifier responds much more slowly. Similarly, during dataverification following a high voltage erase operation, the referencevoltage (V_(ref)) is typically set at 3 volts and an adequately erasedcell has a measured threshold voltage (V_(th)) less than 3 volts. Inthis case, the two inputs of the sense amplifier are also much closerthan in a regular read operation and the sense amplifier's output isagain more susceptible to noise. With noise of sufficient magnitude toproduce a false positive, noise fluctuations will cause the senseamplifier output to be unstable. The output buffer will generate anoutput in response to the fluctuating sense amplifier output. Thisproduces noise on a power supply pin (corresponding to V_(cc), the powersupply voltage, or ground) which is fed back to the sense amplifier.

The noise fed back to the sense amplifier can alter the output of thesense amplifier due to the small noise margin of the data input/outputcircuit when used with data verification reference voltage levels. Thus,while this test mode of data verification is superior to a normal readoperation, it is still susceptible to error owing to the noise producedby the output buffer. Another disadvantage of this externally controlleddata verification procedure is that it requires the test engineer tospecify the address(es) of the memory cells to be verified. Thisincreases the time required to verify the contents of a large number ofmemory cells.

Yet another disadvantage of an externally controlled verificationprocedure which uses the regular read operation sensing path is that itrequires the test engineer to specify the delay between the time theread operation is initiated and when the data indicating the state ofthe cell is read out. This user specified delay is unlikely to match thedelay the internal state machine uses during its internally controlledverification process. The difference between the two time delays canlead to inconsistent results between the two procedures, and hence causedifficulties in correlating the results of the two verificationprocesses.

What is desired is an apparatus which can more accurately verify thestatus of a programmed or erased memory cell than can be obtained byusing a standard read operation. It is also desired that the apparatusnot be susceptible to errors caused by noise introduced by the circuitelements used to perform the verification operation.

SUMMARY OF THE INVENTION

The present invention is directed to a memory system which includesmeans for verifying the contents of a memory cell contained in a memoryarray to determine if a shift in the threshold voltage level hasoccurred. In one embodiment, the memory system is placed into a testmode of operation in which an internal program or erase verify operationis executed under the control of the system's internal state machine.Once in the test mode, the memory system steps through each memory cell,address by address, and reads the contents of the cell using theappropriate reference voltage for a programming or erase operation. Astatus register bit is set indicating successful completion of theverification operation for a block of memory cells. A register bit isalso set if a cell fails the verification operation. The verificationoperation described provides a more accurate determination of the stateof a memory cell than can be achieved by performing an external readoperation using read operation or data verification reference voltagelevels.

Further objects and advantages of the present invention will becomeapparent from the following detailed description and accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram of a conventional non-volatilememory system.

FIG. 2 is a state diagram showing the process flow (sub-operations) of amemory system of the type shown in FIG. 1 during the pre-programming,high voltage erase, and distribution adjustment stages of a completeerase operation.

FIG. 3 is a block diagram of a prior art data input/output circuit forprogramming memory cells of a non-volatile memory array, and for readingdata indicative of the state of those cells.

FIG. 4 is a state diagram showing the process flow of the internalprogram or erase verify operation of the present invention.

FIG. 5 is a schematic of a circuit for a detector/decoder which can beincorporated into a memory system and used for entering a test mode ofoperation in which code signal(s) used to initiate the internal dataverification mode can be input.

FIG. 6 is a functional block diagram of a memory system which includes aflow control register for altering the process flow of the operationsand sub-operations carried out by the system's internal state machine.

FIGS. 7A and 7B show the contents of two embodiments of a flow controlregister of the type shown in FIG. 6.

FIG. 8 shows a set of logic gates which can be used in conjunction witha flow control register control signal to automatically provide signalsto cause a state machine to implement an internal program verify mode byskipping the desired cycles or stages of a complete erase operation.

FIG. 9 shows a set of logic gates which can be used in conjunction witha flow control register control signal to automatically provide signalsto cause a state machine to implement an internal erase verify mode byskipping the desired cycles or stages of a complete erase operation.

DETAILED DESCRIPTION OF THE INVENTION

The inventor of the present invention has recognized that the accuracy,noise, and correlation problems inherent in performing an external dataverification operation using a read operation can be overcome byperforming an internal data verification operation under the control ofa memory system's internal state machine. This can be achieved byplacing the memory system into an internal verify test mode and thenexecuting a data verification operation in which the memory cells areread and their state determined using a programming or erase operationreference voltage level. This provides a more accurate determination ofthe threshold voltage of the memory cells then can be obtained using anormal read operation reference voltage level. In addition, thisverification method is not subject to the noise problems which occurwhen executing an external read operation. Furthermore, since theinternal state machine uses the same timing sequence for the internalverify test mode as for the normal data verification process, theproblem of correlating the results obtained from the two processes doesnot arise. The result is a data verification method which is moreconsistent with the internal verification operation which is executedduring the cycles of a complete erase operation.

FIG. 4 is a state diagram showing the process flow of the internalprogram or erase verify operation of the present invention. As has beendiscussed, the internal data verification operations performed by amemory system of the type shown in FIG. 1 involve determining whether amemory cell conducts current for a given reference voltage. In effect,this is determining whether the threshold voltage of the cell fallsabove or below the reference voltage.

As shown in FIG. 4, once the memory system is placed into the internalverify test mode, the internal state machine causes the memory system toenter the internal program/erase verify mode at stage 400. The addresscounter (element 52 of FIG. 1) which determines the address of thememory cell operated on is reset at stage 402. A read (data compare)operation is then performed on the memory cell at stage 404. The readoperation is performed using the sense amplifier circuitry of FIG. 1,but with the reference voltage set to either the program or erase statereference level, depending on the specified test mode. The data to whichthe read data is compared is obtained from input data latch 30. It isnoted that the data contained in latch 30 can be all zeros (as in apre-programming verify operation), all ones (as in an erase verifyoperation), or a set of user provided data. If the memory cell passesthe read operation (the threshold voltage margin of the cell isappropriate when compared to the program or erase state referencevoltage), then control is passed to stage 406 where the memory celladdress is incremented. If the maximum cell address for memory cells ina block of cells has not been reached, control is passed back to stage404 and the read operation is performed on the cell corresponding to thenew address.

If the memory cell fails the read operation, control is passed to stage408 where a status register bit signifying an error in the dataverification operation is set and the verification operation on theblock of cells is terminated. When all of the memory cells in a block ofcells successfully pass the verification operation and the maximum celladdress for memory cells in the block of cells is reached (the addresscounter is set to maximum address plus one), control is passed to stage408 where a status register bit signifying successful completion of thedata verification operation is set. The setting of a bit in the statusregister indicating the success or failure of the internal verificationoperation permits a test engineer to monitor the outcome of theoperation without having to check whether each memory cell individuallypasses or fails the verification procedure.

The internal data verification mode of FIG. 4 is accessed by placing thememory system into a test mode of operation and then entering theappropriate code(s) to cause the internal state machine to executeeither the program or erase verify mode. This differentiates theinternal verification test mode of the present invention from the normaldata verification procedures which occur during the complete erase cycleof FIG. 2. One method for placing the memory system into a test orspecial mode of operation is described in U.S. Pat. No. 5,526,364,entitled, Apparatus for Entering and Executing Test Mode Operations forMemory, issued Jun. 11, 1996, the contents of which is herebyincorporated in full by reference.

FIG. 5 is a schematic of a circuit for a detector/decoder (see element102 of FIG. 6) which can be incorporated into a memory system and usedfor entering a test mode of operation in which code signal(s) used toinitiate the internal data verification mode can be input. In order toplace the memory system into a mode of operation in which the internaldata verification operation is executed, the test mode must be enteredand the test mode command signals corresponding to the appropriateinternal verify mode must be applied to the data I/O terminals of thememory.

Typically, the end user of the memory system would have no reason tocause the memory system to enter a test or special mode of operationsince this mode is intended to be used by test engineers at the memoryfabrication facility. Furthermore, accidental entry into such a mode isto be avoided since the memory could be rendered permanently inoperablein this mode. Thus, the test mode entry circuitry of FIG. 5 is designedto reduce the likelihood of accidental entry into the mode by requiringsimultaneous application of high voltages to multiple memory systemterminals.

The circuit of FIG. 5 is activated by application of a high voltage totwo or more terminals 700 and 702 of the memory system from an externalsource. These terminals are non-dedicated terminals used during normalmemory operations. Terminals 700 and 702 may include, for example,address terminal (pad) A10 and the write enable terminal {overscore(WE)}. The magnitude of the high voltage applied to terminals 700 and702 is chosen to be outside of the range of voltages which wouldtypically be applied to those terminals during use of the terminals innormal (non-test mode) operation of the memory system. This is done toprevent an end user from unintentionally entering the test or specialmode. The high voltage applied to terminals 700 and 702 is detected bydetectors 706 and 708. A detector circuit suited for use in constructingdetectors 706 and 708 is described in U.S. Patent Application Ser. No.08/493,162, entitled “Integrated Circuit Having High Voltage DetectionCircuit”, filed Jun. 21, 1995, the contents of which is herebyincorporated in full by reference.

After application of high voltage to terminals 700 and 702, a signal onanother terminal 710, in this case the chip enable {overscore (CE)}terminal, is made active (low). Code signal data corresponding to one ofseveral possible test or special modes is placed on the data I/Oterminals 712 of the memory system and forwarded to an I/O buffer 714.In the present case, code data corresponding to an internal data verifyoperation would be input. Note that data I/O terminals 712 and I/Obuffer 714 of FIG. 5 correspond, respectively, to data I/O pins 15 andinput buffer 22 of FIG. 1.

An AND gate 716 provides a test mode load enable signal when the outputsof both high voltage detectors 706 and 708 indicate that an appropriatehigh voltage is being applied to terminals 700 and 702. The load enablesignal is coupled to one input of an AND gate 718 together with aninverted signal {overscore (CE)}. This causes AND gate 718 to turn onpass transistor 720 which forwards the test or special mode code dataentered by means of I/O pads 712 to buffer 714 and then to a test modecode latch 722. Separate I/O terminals and pass transistors 720 are usedfor each bit of input test or special mode data so that the data will beloaded into latch 722 in parallel. Typically there are a total of eightbits of test code data so that latch 722 will contain eight bits. Signal{overscore (CE)} is then brought back to a high state, thereby latchingthe code data in latch 722.

After latch 722 has been loaded with the code data, one of the highinput voltages, such as the input to address A10 terminal 702 is removedso that the output of detector 708 will go low thereby providing a highinput to an AND gate 730 by way of inverter 728. Since the remaininginput of gate 730, the output of the second high voltage detector 706,will still be high, gate 730 will produce a test or special mode enablesignal. Among other things, this will enable a Test Mode and FormatCheck and Decode Logic unit 724 which will verify that the data in latch722 corresponds to a proper test or special mode. In addition, unit 724will decode the mode code to determine which one of approximatelyfifteen different special or test modes has been entered. These modeseach have an associated mode signal which is produced by the Test Modeand Format Check and Decode Logic unit 724 and which is used by thememory system in combination with other signals for carrying out thevarious test or special mode functions.

The system will remain in the selected mode as long as the voltageapplied to terminal 700 remains high. When signal {overscore (CE)} isbrought back to a high state, detector activation logic 732 keepsdetector circuits 704 and 706 enabled as long as the voltage applied toterminal 700 remains high. During the course of carrying out the varioustest or special mode operations, it may be necessary to periodicallychange the state of the chip enable {overscore (CE)} signal. However,since address A10 on line 702 has been shifted to a low state, the lowoutput of AND gate 718 will prevent any change in the contents of modecode latch 722. Once the test or special mode of operation is completed,the high voltage applied to terminal 700 is removed, thereby causing theoutput of AND gate 730 to go low and end the test or special mode ofoperation.

The test mode codes loaded into latch 722 are preferably of a specificformat which further reduces the possibility of accidental entry into atest mode. The mode code is typically divided into two groups of bits,with the first group of bits, the format bits, signifying a test orspecial mode of operation and the remaining bits signifying a particularone of the modes. A description of a code format suited for use with thepresent invention can be found in the previous mentioned U.S. Pat. No.08/386,704, entitled, “Apparatus for Entering and Executing Test ModeOperations for Memory”.

With regards to the present invention, after placing the memory systeminto a test or special mode by using the appropriate type and sequenceof high voltage signals, a user would enter test code(s) or signalscorresponding to an internal program or erase verify test mode. Thiswill cause the memory system's internal state machine to execute theinternal data verification operation shown in FIG. 4 with theappropriate reference voltage. This will result in stepping through thememory cells, address by address, and verifying that the cells areprogrammed or erased with the proper threshold voltage margins. At theconclusion of the verification process (or during the process, in thecase of a verification error), a status register bit which indicates thesuccess or failure of the data verification operation will be set.

As noted, one method of performing the internal data verify operation ofthe present invention is to execute the process flow of FIG. 4 as anindependent operation. However, it is also possible to execute therelevant stages of the complete erase operation shown in FIG. 2, whileskipping the irrelevant stages. This can be accomplished by instructingthe memory system to disable or skip the appropriate stages of thepre-programming or high voltage erase cycle of the complete eraseoperation. One method for performing this function is described in U.S.Patent Application Ser. No. 08/508,921, entitled “Memory System HavingProgrammable Flow Control Register”, filed Jul. 28, 1995, the contentsof which is hereby incorporated in full by reference.

FIG. 6 is a functional block diagram of a memory system 100 whichincludes a flow control register 110 for altering the process flow ofthe operations and sub-operations carried out by the system's internalstate machine 20. It is noted that FIG. 6 is meant to be suggestive ofthe connections between flow control register 110, its associatedcircuitry 112 and the rest of the memory system, and that not allinterconnections are shown. It is also noted that similar referencenumbers in FIGS. 1 and 6 refer to the same signals and components in thetwo figures.

As with the memory system of FIG. 1, the core of memory system 100 is anarray 12 of memory cells. The individual memory cells (not shown) areaccessed by using an eighteen bit address A0-A17, which is input bymeans of address pins 13. Memory system 100 contains internal statemachine (ISM) 20 which controls the data processing operations andsub-operations performed on memory system 100, such as the stepsnecessary for carrying out programming, reading and erasing operationson the memory cells of array 12. Internal state machine 20 is typicallyimplemented in the form of a set of logic gates whose inputs determinewhich operations and sub-operations of the memory system are carriedout, and in what order those operations occur.

Memory system commands are issued on I/O pins 15, and are transferred todata input buffer 22 and then to command execution logic unit 24.Command execution logic unit 24 receives and interprets the commandsused to initiate and control the steps required for erasing array 12 orcarrying out another desired operation. If a programming operation isbeing executed, the data to be programmed into the memory cells is inputusing I/O pins 15, transferred to input buffer 22, and then placed ininput data latch 30. The data in latch 30 is then made available tosense amplifier circuitry 50 for the programming and data verificationoperations. Once an operation is completed, state machine 20 updates 8bit status register 26. The contents of status register 26 istransferred to data output buffer 28, which makes the contents availableon data I/O pins 15 of memory system 100.

Memory system 100 includes a test mode detector and decoder 102 used forentry into a test or special mode of operation in which the contents offlow control register 110 may be read or altered, and code signals usedfor executing an internal data verification operation may be input.Details of the implementation of the detector/decoder 102 werepreviously described with reference to FIG. 5.

Flow control register 110 contains data used to alter the process flowof the memory system. This is accomplished by instructing internal statemachine 20 to include or bypass certain operations or sub-operations,examples of which are shown in FIG. 2. Individual bits within register110 are used to determine the operations and sub-operations carried outunder control of internal state machine 20. For example, by setting abit or bits of register 110, the flow may be modified to bypass theerase high voltage (step 222 of FIG. 2) or distribution tighteningcycles (step 240 of FIG. 2) of the complete erase operation. If it isdesired to read the contents of control register 110, that data may berouted through test signal switch 104 to output buffer 28 by means ofdata bus 106, and made available to a system designer.

FIGS. 7A and 7B show the contents of two embodiments of flow controlregister 110. It is noted that the difference between the twoembodiments is that in FIG. 7A, bit one is reserved, while in FIG. 7B,bit one is used to skip the high voltage stages of a desired cycle ofthe complete erase operation. As shown in FIGS. 7A and 7B, flow controlregister 110 is implemented as an 8 bit storage medium. Flow controlregister 110 may be implemented in the form of a volatile or anon-volatile storage medium, or a combination of the two. If implementedas a volatile medium, register 110 must be re-programmed each time thesystem is powered up. This can be accomplished by means of flow controlregister circuitry 112. Flow control register 110 may also beimplemented in the form of a storage medium having a volatile and anon-volatile portion. In this case, register 110 would containnon-volatile memory elements which were programmed by circuitry 112 tovalues corresponding to the desired bit values of the flow controlregister. When power is applied to the memory system, the contents ofthe non-volatile portion of the flow control register would be copied tothe volatile portion of the flow control register. This section wouldthen control the operation of the state machine. Further details of amethod of implementing flow control register 110 can be found in thepreviously mentioned U.S. Pat. Application Serial No. 08/508,921,entitled “Memory System Having Programmable Flow Control Register”, andin U.S. Patent Application Ser. No. 08/508,864, entitled, “Non-volatileData Storage Unit and Method of Controlling Same”, filed Jul. 28, 1995,the contents of which is hereby incorporated in full by reference.

The value of each bit of flow control register 110 corresponds to aninstruction to internal state machine 20 to include or bypass theindicated operation or sub-operation, i.e., skip program verify, eraseverify, high voltage stage, etc. Depending on the value of the bits, theindicated cycle or stage in the process flow of the memory system iseither implemented or bypassed. Combination of bits (multiple bits) mayalso be used to instruct the internal state machine to include or bypasscertain operations or sub-operations. It is noted that a memory systemdesigner can place as many bits as necessary in register 110 to createas much flexibility in modifying the operation of the memory system asis desired. It is well known to those skilled in the art how toconstruct a logic circuit which uses the value of the indicated bit(s)of flow control register 110 to alter the operations and sub-operationscarried out by an internal state machine.

One means of conducting a programming operation data verification is touse the pre-programming cycle of a complete erase operation to access amemory cell, verify that a zero has been written to the accessed cell,and then proceed to the next cell. Executing this cycle will also causea bit to be set in the status register indicating the success or failureof the data verification operation carried out during the cycle.Execution of the pre-programming cycle can be accomplished by twomethods, depending upon whether the embodiment of FIG. 7A or 7B of flowcontrol register 110 is used. If the flow control register of FIG. 7A isused, then it is necessary to set the bits of flow control register 110so that the erase high voltage 220 and distribution adjustment 240cycles are skipped. This corresponds to setting bits 7 and 6 of the flowcontrol register shown in FIG. 7A. In addition, it is necessary that thehigh voltage stages of the pre-programming cycle be skipped. This isaccomplished by having the memory system operate so that entry into theprogram verify test mode automatically generates a control signal whichcauses the internal state machine to skip the high voltage stages of thecomplete erase operation. If the pre-programming cycle is then executed(by instructing the internal state machine to execute a complete eraseoperation), the internal state machine will access each memory cell andverify that a zero has been written to the cells.

Similarly, in order to conduct an erase operation data verification, thehigh voltage erase cycle of a complete erase operation can be used toaccess a memory cell, verify that a one has been written to the accessedcell, and then proceed to the next cell. As with the execution of thepre-programming cycle, a bit will be set in the status registerindicating the success or failure of the erase operation dataverification. Execution of the high voltage erase cycle can beaccomplished by setting the bits of flow control register 110 so thatthe pre-programming 200 and distribution adjustment 240 cycles areskipped. This corresponds to setting bits 8 and 6 of the flow controlregister embodiment of FIG. 7A. In addition, it is necessary that thehigh voltage stages of the high voltage erase cycle be skipped. Asdiscussed, this is accomplished by having the memory system operate sothat entry into the erase verify test mode automatically generates acontrol signal which causes the internal state machine to skip the highvoltage stages of the complete erase operation. If the high voltageerase cycle is then executed (by instructing the internal state machineto execute a complete erase operation), the internal state machine willaccess each memory cell and verify that a one has been written to thecells.

In the embodiments of the present invention just discussed, the user isresponsible for entering the program or erase verify test mode andsetting the contents of flow control register 110 to the appropriatevalues for skipping the desired cycles and/or stages of the completeerase operation. However, this function may also be executedautomatically upon entry into the test mode and input of the appropriateinternal verify code. This is accomplished by having Test Mode andFormat Check and Decode Logic unit 724 of detector/decoder 102 produce aflow control register control signal (signal 501 or 502 of FIGS. 3, 8,and 9) when the internal verify test mode is entered. Flow controlregister control signal 501 or 502 (or the inverted signal) serves as afirst input to a set of logic gates, with the other input to each gatebeing the value of one of the bits of flow control register 110. Theoutputs of the logic gates serve as the control signals to the statemachine to cause the desired cycles or stages of a complete eraseoperation to be skipped.

FIG. 8 shows a set of logic gates 500 which can be used in conjunctionwith flow control register control signal 501 to automatically providesignals 504 to cause state machine 20 to implement an internal programverify mode by skipping the desired cycles or stages of a complete eraseoperation. As shown in the figure, logic gates 500 comprise a set oftwo-input OR gates (gates 506, 508, 510, 514, and 516) and two-input ANDgates 512 and 518. A first input to each logic gate 500 is a signalrepresenting the contents of each bit of flow control register 110.Thus, one input to each logic gate 500 is a high (logic 1) or low (logic0) value corresponding to the value of each bit of register 110. Thesecond input to each logic gate 500 is flow control register controlsignal 501 or an inverted version of that signal. The inverted versionis provided by an inverter 520 placed in the signal path between signal501 and the second input to the appropriate logic gate 500. The internalstate machine logic is such that when a control signal 504 produced by alogic gate 500 is high, the cycle or stage corresponding to the input tothat logic gate is skipped. For example, if output signal 504 of OR gate508 is high, then the program verify stage is skipped. With flow controlregister control signal 501 high, the outputs of each of the OR gateswill be high. As a result, the cycles or stages corresponding to thesecond input to those gates will be skipped. For the purposes of theinternal program verify mode it is desired to skip the erase highvoltage and distribution tightening cycles, as well as the erase verify,program verify, and final erase stages of the complete erase operation.Thus, it is desired that the outputs 504 of logic gates 506, 508, 510,514, and 516 be high. This will cause state machine 20 to skip thedesired operations.

Conversely, because of the use of inverter 520, when signal 501 goeshigh (indicating that the internal program verify mode has beenentered), one input to AND gates 512 and 518 is low. Therefore, outputsignal 504 of AND gates 512 and 518 is low and the corresponding cycleor stage (in this case the pre-programming cycle and pre-programmingverify stage) are not skipped and instead are implemented. With thearrangement of logic gates shown in FIG. 8, when flow control registersignal 501 goes high, the outputs 504 of logic gates 500 will causestate machine 20 to implement the pre-programming cycle andpre-programming verify stage and skip the other cycles and stages of thecomplete erase operation. It is noted that as previously discussed,entry into the internal data verification test mode also acts togenerate a control signal which causes the high voltage stages of thepre-programming cycle to be skipped. These actions will result inexecuting the internal program verify test mode of the presentinvention. The use of logic gates 500 and inverter 520 allows automaticcontrol of the cycles and stages of the complete erase operation whichare implemented when the internal verify mode is entered.

FIG. 9 shows a set of logic gates 500 which can be used in conjunctionwith flow control register control signal 502 to automatically providesignals 504 to cause state machine 20 to implement an internal eraseverify mode by skipping the desired cycles or stages of a complete eraseoperation. As shown in the figure, logic gates 500 comprise a set oftwo-input OR gates (gates 506, 508, 512, 514, and 518) and two-input ANDgates 510 and 516. As with FIG. 8, a first input to each logic gate 500is a signal representing the contents of each bit of flow controlregister 110. The second input to each logic gate 500 is flow controlregister control signal 502 or an inverted version of that signal whichis provided by an inverter 520 placed in the signal path between signal502 and the second input to the appropriate logic gate 500. Again it isassumed that the internal state machine logic is such that when acontrol signal 504 produced by a logic gate 500 is high, the cycle orstage corresponding to the input to that logic gate is skipped. Withflow control register control signal 502 high, the outputs of each ofthe OR gates will be high. As a result, the cycles or stagescorresponding to the second input to those gates will be skipped. Forthe purposes of the internal erase verify mode it is desired to skip thepre-programming and distribution tightening cycles, as well as thepre-program verify, program verify, and final erase stages of thecomplete erase operation. Thus, it is desired that the outputs 504 oflogic gates 506, 508, 512, 514, and 518 be high. This will cause statemachine 20 to skip the desired operations.

Conversely, because of the use of inverter 520, when signal 502 goeshigh (indicating that the internal erase verify mode has been entered),one input to AND gates 512 and 518 is low. Therefore, output signal 504of AND gates 510 and 516 is low and the corresponding cycle or stage (inthis case the high voltage erase cycle and erase verify stage) are notskipped and instead are implemented. With the arrangement of logic gatesshown in FIG. 9, when flow control register signal 502 goes high, theoutputs 504 of logic gates 500 will cause state machine 20 to implementthe high voltage erase cycle and erase verify stage and skip the othercycles and stages of the complete erase operation. It is noted that aspreviously discussed, entry into the internal data verification testmode also acts to generate a control signal which causes the highvoltage stages of the high voltage erase cycle to be skipped. Theseactions will result in executing the internal erase verify test mode ofthe present invention.

If the flow control register of FIG. 7B is used, then it is necessary toset the bits of flow control register 110 so that the erase high voltage220 and distribution adjustment 240 cycles, and the high voltage stagesof the pre-programming cycle are skipped in order to execute a programverify operation. This corresponds to setting bits 7, 6, and 1 of flowcontrol register 110. A complete erase operation is then executed. It isnoted that this means of executing the internal data verificationprocedure does not require placing the memory system into a separateinternal verify test mode of operation.

Similarly, if the flow control register of FIG. 7B is used, it isnecessary to set the bits of flow control register 110 so that thepre-programming 200 and distribution adjustment 240 cycles, and the highvoltage stages of the erase cycle are skipped in order to execute anerase verify operation. This corresponds to setting bits 8, 6, and 1 offlow control register 110. A complete erase operation is then executed.It is noted that this means of executing the internal data verificationprocedure does not require placing the memory system into a separateinternal verify test mode of operation.

As noted, in order to conduct a programming operation data verificationwhich verifies that a zero has been written to each memory cell, amodified version of the pre-programming cycle can be executed.Similarly, a modified version of the high voltage erase operation can beexecuted in order to verify that a one has been written to each memorycell. However, it may also be desired to conduct an internal dataverification procedure in which the presence of data other than a zeroor one in every cell is verified.

In the case of a data verification operation using data specified by atest engineer, this goal can be accomplished by setting the bits of theembodiment of flow control register 110 of FIG. 7B so that the highvoltage erase 220 and distribution adjustment 240 cycles of the completeerase operation, and the high voltage stages of the pre-programmingcycle are skipped. The memory system is then placed into a test mode inwhich user specified data is placed into input data latch 30 and thepre-programming cycle is executed using that data for verificationpurposes.

One means of providing the desired data for an internal dataverification operation is described in U.S. Patent Application08/589,754, entitled “Non-volatile Memory System-Including Apparatus forTesting Memory Elements by Writing and Verifying Data Patterns”, filedthe same day as this application, the contents of which is herebyincorporated in full by reference. By entering the external patternwrite test mode described in the above-identified application, datainput to I/O pins 15 is placed into data latch 30 and used during thedata verification mode of the present invention. By executing theremaining stages of the pre-program cycle (by executing the completeerase operation), the internal program verification mode of FIG. 4 willbe carried out using the user specified data. The combination of usingthe flow control register of FIG. 7B and the external pattern test modepermits the internal data verification mode of the present invention tobe executed using data other than all ones or all zeros.

The terms and expressions which have been employed herein are used asterms of description and not of limitation, and there is no intention inthe use of such terms and expressions of excluding equivalents of thefeatures shown and described, or portions thereof, it being recognizedthat various modifications are possible within the scope of theinvention claimed.

I claim:
 1. A memory system having a standard mode of operation in whicha user can program, erase, and read a memory cell, and a test mode ofoperation in which a non-standard mode of operation can be executed,wherein access to the test mode of operation occurs upon detection of atest mode access state different from those states which occur duringthe standard mode of operation, the memory system comprising: an arrayof memory cells; a test mode detector which detects the test mode accessstate, wherein the test mode access state is different from those stateswhich occur during the standard mode of operation; an internal programverify circuit which executes an internal program verify operation whenthe memory system is placed into an internal program verify mode ofoperation by the test mode detector, wherein the internal program verifycircuit further comprises a memory cell accessor which accesses a memorycell in the array; a programmed data verification circuit which verifiesdata programmed into the memory cell; and an address incrementer whichincrements an address of the memory cell; and a test mode statusindicator accessible to a user of the test mode which indicates successor failure of the operation executed when the memory system is placedinto the internal program verify mode of operation by the test modedetector.
 2. The memory system of claim 1, wherein the programmed dataverification circuit further comprises: a threshold voltage circuitwhich determines a threshold voltage of the memory cell; and acomparator which compares the threshold voltage to a program operationreference voltage.
 3. The memory system of claim 1, further comprising:a controller for controlling execution of a memory erase operation whichincludes a plurality of memory erase sub-operations, the memory erasesub-operations including a regular memory pre-programming operationwhich accesses a memory cell in the array, programs the accessed memorycell with data indicative of a logic value of zero, verifies theprogrammed data, increments the address of the memory cell, and executesthe regular pre-programming operation on a memory cell having an addresscorresponding to the incremented address, wherein the internal programverify circuit further comprises: a flow controller for causing thecontroller to bypass one of the plurality of memory erasesub-operations.
 4. The memory system of claim 3, wherein the flowcontroller bypasses the memory erase sub-operation in response tocontrol parameters stored in a data storage element of the memorysystem.
 5. The memory system of claim 4, further comprising: a controlparameter generator which generates the control parameters for bypassingthe erase sub-operation in response to a control signal which initiatesexecution of the internal program verify operation.
 6. The memory systemof claim 3, wherein the flow controller bypasses a memory erasesub-operation not involved in the internal program verify operation. 7.The memory system of claim 3, wherein the memory system executes a highvoltage stage in which a high voltage pulse is applied to a memory cellduring a pre-programming operation, and wherein the test mode detectorfurther comprises: a high voltage control signal generator whichgenerates a high voltage stage control signal which causes the highvoltage stage to be bypassed when the memory system is placed into aninternal program verify mode of operation by the test mode detector. 8.A memory system having a standard mode of operation in which a user canprogram, erase, and read a memory cell, and a test mode of operation inwhich a non-standard mode of operation can be executed, wherein accessto the test mode of operation occurs upon detection of a test modeaccess state different from those states which occur during the standardmode of operation, the memory system comprising: an array of memorycells; a test mode detector which detects the test mode access state,wherein the test mode access state is different from those states whichoccur during the standard mode of operation; an internal erase verifycircuit which executes an internal erase verify operation when thememory system is placed into an internal erase verify mode of operationby the test mode detector, wherein the internal erase verify circuitfurther comprises a memory cell accessor which accesses a memory cell inthe array; an erase verification circuit which verifies that the memorycell has been erased; and an address incrementer which increments anaddress of the memory cell; and a test mode status indicator accessibleto a user of the test mode which indicates success or failure of theoperation executed when the memory system is placed into the internalerase verify mode of operation by the test mode detector.
 9. The memorysystem of claim 8, wherein the erase verification circuit furthercomprises: a threshold voltage circuit which determines a thresholdvoltage of the memory cell; and a comparator which compares thethreshold voltage to an erase operation reference voltage.
 10. Thememory system of claim 8, further comprising: a controller forcontrolling execution of a memory erase operation which includes aplurality of memory erase sub-operations, the memory erasesub-operations including a regular memory high voltage erase operationin which a high voltage erase operation is performed on a block ofmemory cells, a memory cell in the block is accessed, an erased state ofthe accessed memory cell is verified, the address of the memory cell isincremented, and the erased state verification operation is performed ona memory cell having an address corresponding to the incrementedaddress, wherein the internal erase verify circuit further comprises: aflow controller for causing the controller to bypass one of theplurality of memory erase sub-operations.
 11. The memory system of claim10, wherein the flow controller bypasses the memory erase sub-operationin response to control parameters stored in a data storage element ofthe memory system.
 12. The memory system of claim 11, furthercomprising: a control parameter generator which generates the controlparameters for bypassing the erase sub-operation in response to acontrol signal which initiates execution of the internal erase verifyoperation.
 13. The memory system of claim 10, wherein the flowcontroller bypasses a memory erase sub-operation not involved in theinternal erase verify operation.
 14. The memory system of claim 10,wherein the memory system executes a high voltage stage in which a highvoltage pulse is applied to a memory cell during an erase operation, andwherein the test mode detection means further comprises: a high voltagecontrol signal generator which generates a high voltage stage controlsignal which causes the high voltage stage to be bypassed when thememory system is placed into an internal erase verify mode of operationby the test mode detector.
 15. A memory system comprising: an array ofmemory cells; a controller for controlling execution of a memory eraseoperation which includes a plurality of memory erase sub-operations, thememory erase sub-operations including a regular memory pre-programmingoperation which accesses a memory cell in the array, programs theaccessed memory cell with data indicative of a logic value of zero,verifies the programmed data, increments the address of the memory cell,and executes the regular pre-programming operation on a memory cellhaving an address corresponding to the incremented address; and acontrol modifier which modifies the operation of the controller to causethe controller to execute an internal program verify operation on thememory cells of the memory array, the internal program verify operationincluding accessing a memory cell in the array, verifying dataprogrammed into the memory cell, and incrementing an address of thememory cell.
 16. The memory system of claim 15, further comprising: aninternal program verify modifier which modifies execution of theinternal program verify operation so that the data programmed into thecell which is verified is data input by a user.
 17. A memory systemcomprising: an array of memory cells; a controller for controllingexecution of a memory erase operation which includes a plurality ofmemory erase sub-operations, the memory erase sub-operations including aregular memory high voltage erase operation in which a high voltageerase operation is performed on a block of memory cells, a memory cellin the block is accessed, an erased state of the accessed memory cell isverified, the address of the memory cell is incremented, and, the erasedstate verification operation is performed on a memory cell having anaddress corresponding to the incremented address; and a control modifierwhich modifies the operation of the controller to cause the controllerto execute an internal erase verify operation on the memory cells of thememory array, the internal erase verify operation including accessing amemory cell in the array, verifying that the memory cell has beenerased, and incrementing an address of the memory cell.
 18. A method ofverifying a state of a memory cell contained in a memory array of amemory system, the memory system having a standard mode of operation inwhich a user can program, erase, and read a memory cell and a test modeof operation in which a non-standard mode of operation can be executed,wherein access to the test mode of operation occurs upon detection of atest mode access state different from those states which occur duringthe standard mode of operation, the method comprising: accessing thetest mode of operation; placing the memory system into an internalprogram verify mode of operation; executing an internal program verifyoperation when the memory system is placed into the internal programverify mode of operation, wherein the step of executing the internalprogram verify operation further comprises accessing a memory cell inthe array; verifying data programmed into the memory cell; andincrementing an address of the memory cell; and setting a bit of a testmode status register accessible to a user of the test mode indicatingsuccess or failure of the internal program verify operation.
 19. Themethod of claim 18, wherein the step of verifying data programmed intothe memory cell further comprises: determining a threshold voltage ofthe memory cell and comparing it to a program operation referencevoltage.
 20. The method of claim 18, wherein the memory system includesa controller for controlling execution of a memory erase operation whichincludes a plurality of memory erase sub-operations, the memory erasesub-operations including a regular memory pre-programming operationwhich accesses a memory cell in the array, programs the accessed memorycell with data indicative of a logic value of zero, verifies theprogrammed data, increments the address of the memory cell, and executesthe regular pre-programming on a memory cell having an addresscorresponding to the incremented address, and wherein the method furthercomprises: causing the controller to bypass a memory erase sub-operationnot involved in the internal program verify operation.
 21. The method ofclaim 20, wherein the step of causing the controller to bypass a memoryerase sub-operation further comprises: generating a control signal whichcauses the controller to bypass the memory sub-operation in response toplacing the memory system into an internal program verify mode ofoperation.
 22. A method of verifying a state of a memory cell containedin a memory array of a memory system, the memory system having astandard mode of operation in which a user can program, erase, and reada memory cell and a test mode of operation in which a non-standard modeof operation can be executed, wherein access to the test mode ofoperation occurs upon detection of a test mode access state differentfrom those states which occur during the standard mode of operation, themethod comprising: accessing the test mode of operation; placing thememory system into an internal erase verify mode of operation; executingan internal erase verify operation when the memory system is placed intoan internal erase verify mode of operation, wherein the step ofexecuting the internal erase verify operation further comprisesaccessing a memory cell in the array; verifying that the memory cell hasbeen erased; and incrementing an address of the memory cell; and settinga bit of a test mode status register accessible to a user of the testmode indicating success or failure of the internal erase verifyoperation.
 23. The method of claim 22, wherein the step of verifyingthat the memory cell has been erased further comprises: determining athreshold voltage of the memory cell and comparing it to an eraseoperation reference voltage.
 24. The method of claim 22, wherein thememory system includes a controller for controlling execution of amemory erase operation which includes a plurality of memory erasesub-operations, the memory erase sub-operations including a regularmemory high voltage erase operation in which a high voltage eraseoperation is performed on a block of memory cells, a memory cell in theblock is accessed, an erased state of the accessed memory cell isverified, the address of the memory cell is incremented, and the erasedstate verification operation is performed on a memory cell having anaddress corresponding to the incremented address, and wherein the methodfurther comprises: causing the controller to bypass a memory erasesub-operation not involved in the internal erase verify operation. 25.The method of claim 24, wherein the step of causing the controller tobypass a memory erase sub-operation further comprises: generating acontrol signal which causes the controller to bypass the memorysub-operation in response to placing the memory system into an internalerase verify mode of operation.
 26. A method of verifying a state of amemory cell contained in a memory array of a memory system, the memorysystem including a controller which controls execution of a memory eraseoperation which includes a plurality of memory erase sub-operations, thememory erase sub-operations including a regular memory pre-programmingoperation which accesses a memory cell in the array, programs theaccessed memory cell with data indicative of a logic value of zero,verifies the programmed data, increments the address of the memory cell,and executes the regular pre-programming on a memory cell having anaddress corresponding to the incremented address, the method comprising:causing the controller to bypass the memory sub-operations not involvedin an internal program verify operation; and executing an internalprogram verify operation, wherein the step of executing the internalprogram verify operation further comprises: accessing a memory cell inthe array; verifying data programmed into the memory cell; andincrementing an address of the memory cell.
 27. The method of claim 26,wherein the step of verifying data programmed into the memory cellfurther comprises: determining a threshold voltage of the memory celland comparing it to a program operation reference voltage.
 28. Themethod of claim 26, wherein the step of executing an internal programverify operation further comprises: setting a status register bitindicating success or failure of the internal program verify operation.29. A method of verifying a state of a memory cell contained in a memoryarray of a memory system, the memory system including a controller whichcontrols execution of a memory erase operation which includes aplurality of memory erase sub-operations, the memory erasesub-operations including a regular memory high voltage erase operationin which a high voltage erase operation is performed on a block ofmemory cells, a memory cell in the block is accessed, an erased state ofthe accessed memory cell is verified, the address of the memory cell isincremented, and the erased state verification operation is performed ona memory cell having an address corresponding to the incrementedaddress, the method comprising: causing the controller to bypass thememory sub-operations not involved in an internal erase verifyoperation; and executing an internal erase verify operation, wherein thestep of executing the internal erase verify operation further comprises:accessing a memory cell in the array; verifying that the memory cell hasbeen erased; and incrementing an address of the memory cell.
 30. Themethod of claim 29, wherein the step of verifying that the memory cellhas been erased further comprises: determining a threshold voltage ofthe memory cell and comparing it to an erase operation referencevoltage.
 31. The method of claim 29, wherein the step of executing aninternal erase verify operation further comprises: setting a statusregister bit indicating success or failure of the internal erase verifyoperation.
 32. A memory system comprising: an array of memory cells; acontroller coupled to the array for performing a plurality of memoryoperations on the array of memory cells including an internal memoryverification operation; and an externally available status indicatorcoupled to the controller, wherein the controller sets the statusindicator to indicate success or failure of the internal memoryverification operation during a memory test operation, wherein thecontroller bypasses at least one memory sub-operation in order toperform the internal memory verification operation.
 33. The memorysystem of claim 32 and further including a comparator for comparing asensed voltage of a selected memory cell to a reference voltage, whereinthe controller sets the status indicator as a function of thecomparison.
 34. The memory system of claim 33, wherein the comparatorcompares the sensed voltage of the selected cell to a program referencevoltage.
 35. The memory system of claim 33, wherein the comparatorcompares the sensed voltage of the selected cell to an erase referencevoltage.
 36. The memory system of claim 32, wherein the controllerperforms each of the plurality of memory operations by executing one ormore memory sub-operations according to control parameters stored in adata storage element of the memory system.
 37. A memory systemcomprising: an array of memory cells; a controller coupled to the arrayfor performing a plurality of memory operations on the array of memorycells including an internal memory verification operation; and anexternally available status indicator coupled to the controller, whereinthe controller sets the status indicator to indicate success or failureof the internal memory verification operation, the controller performseach of the plurality of memory operations by executing one or morememory sub-operations according to a user-configurable flow, and thecontroller bypasses at least one of the memory sub-operations in orderto perform the internal memory verification operation.
 38. The memorysystem of claim 37, wherein the controller bypasses the memorysub-operations in response to a user configurable control parameterstored in a data storage element of the memory system.
 39. The memorysystem of claim 37, wherein the controller bypasses a memory erasesub-operation in order to perform a program-verify memory operation. 40.The memory system of claim 37, wherein the controller bypasses a memorypre-programming sub-operation in order to perform an erase-verify memoryoperation.
 41. A memory device comprising: an array of memory cells; anda controller coupled to the array, wherein the controller performs eachof a plurality of memory operations on the array by bypassing one ormore memory sub-operations according to a user-configurable flowregister in order to perform an internal memory verification.
 42. Thememory device of claim 41 and further including an externally availablestatus indicator coupled to the controller, wherein the controller setsthe status indicator to indicate success or failure of an internalmemory verification operation.
 43. The memory device of claim 42 andfurther including a comparator for comparing a sensed voltage of aselected memory cell to a reference voltage, wherein the controller setsthe status indicator according to the comparison.
 44. The memory deviceof claim 43, wherein the comparator compares the sensed voltage of theselected cell to a program reference voltage.
 45. The memory device ofclaim 43, wherein the comparator compares the sensed voltage of theselected cell to an erase reference voltage.
 46. A memory devicecomprising: an array of memory cells; and a controller coupled to thearray, wherein the controller performs each of a plurality of memoryoperations on the array by executing one or more memory sub-operationsaccording to a user-configurable flow register, wherein the controllerbypasses at least one of the memory sub-operations in order to performan internal memory verification operation in response to a controlparameter stored in a data storage element of the memory device.
 47. Thememory device of claim 46, wherein the controller bypasses a memoryerase sub-operation in order to perform a program-verify memoryoperation.
 48. The memory device of claim 46, wherein the controllerbypasses a memory pre-programming sub-operation in order to perform anerase-verify memory operation.
 49. A method of internally verifying amemory device comprising: initiating an internal memory verificationoperation, during a test operation, based on a user-configurable controlparameter; comparing a sensed voltage of a selected cell with areference voltage during the memory verification operation; and settingan externally available status indicator to indicate success or failureof the comparison.
 50. The method of claim 49, wherein comparing thesensed voltage of the selected memory cell includes comparing the sensedvoltage to a program reference voltage.
 51. The method of claim 49,wherein comparing the sensed voltage of the selected memory cellincludes comparing the sensed voltage to an erase reference voltage. 52.The method of claim 49, wherein initiating the internal memoryverification operation includes executing one or more memorysub-operations using according to a user-configurable flow controller.53. A method of internally verifying a memory device comprising:initiating an internal memory verification operation based on auser-configurable control parameters stored in a data storage element ofthe memory device; comparing a sensed voltage of a selected cell with areference voltage during the memory verification operation; and settingan externally available status indicator to indicate success or failureof the comparison, wherein initiating the internal memory verificationoperation includes executing one or more memory sub-operations accordingto a user-configurable sequence, and wherein executing the memorysub-operations includes bypassing at least one of the memorysub-operations in response to the user configurable control parameterstored in a data storage element of the memory device.
 54. The method ofclaim 53, wherein bypassing at least one of the memory sub-operationsincludes bypassing a memory erase sub-operation in order to perform aprogram-verify memory operation.
 55. The method of claim 53, whereinbypassing at least one of the memory sub-operations includes bypassing amemory pre-programming sub-operation in order to perform an erase-verifymemory operation.
 56. A method of internally verifying a memory devicecomprising: initiating an internal memory verification operation basedon a user-configurable control parameter; comparing a sensed voltage ofa selected cell with a reference voltage during the memory verificationoperation; and setting an externally available status indicator toindicate success or failure of the comparison, wherein comparing thesensed voltage includes setting the reference level as a function ofdata stored in a reference level register.
 57. A method of performing aninternal memory verification operation on a memory device comprising:performing one or more memory operations during a normal mode byexecuting a plurality of memory sub-operations in a sequence; andperforming an internal memory verification operation during a test modeby executing a subset of the memory sub-operations, wherein performingthe internal memory verification operation includes executing the subsetof memory sub-operations according to a user-configurable controlparameter stored in a data storage element of the memory device.
 58. Amethod of performing an internal memory verification operation on amemory device comprising: performing one or more memory operationsduring a normal mode by executing a plurality of memory sub-operationsin a sequence; and performing an internal memory verification operationduring a test mode by executing a subset of the memory sub-operations,wherein performing the internal memory verification operation includesexecuting the subset of memory sub-operations according to auser-configurable control parameter stored in a data storage element ofthe memory device, wherein executing the subset of memory sub-operationsincludes bypassing at least one of the memory sub-operations in responseto the user configurable control parameter.
 59. The method of claim 58,wherein bypassing at least one of the memory sub-operations includesbypassing a memory erase sub-operation in order to perform aprogram-verify memory operation.
 60. The method of claim 58, whereinbypassing at least one of the memory sub-operations includes bypassing amemory pre-programming sub-operation in order to perform an erase-verifymemory operation.
 61. The method of claim 58, wherein performing theinternal memory verification operation includes setting an externallyavailable status indicator as a function of the comparison.
 62. A memorysystem, comprising: an internal state machine adapted to perform memoryoperations by sequentially executing memory sub-operations, wherein atleast one memory operations involves verification of a memory cellvoltage level; and a flow register having data fixing the sequence ofthe memory sub-operations executed by the internal state machine,wherein the data of the flow register is a function of controlparameters stored in a data storage element of the memory system. 63.The system of claim 62 and further including: a comparator for comparingthe cell voltage level with a reference voltage level; and a useravailable status indicator, wherein the internal state machine sets theindicator as a function of the comparator.
 64. The system of claim 63,wherein the reference voltage level corresponds to a programmed cellvoltage level.
 65. The system of claim 63, wherein the reference voltagelevel corresponds to an erased cell voltage level.
 66. The system ofclaim 63, wherein the reference voltage level is data input by a user.67. A system, comprising: a processor; and a memory device connected tothe processor, comprising: an array of memory cells; a controllercoupled to the array for performing a plurality of memory operations onthe array of memory cells including an internal memory verificationoperation; and an externally available status indicator coupled to thecontroller, wherein the controller sets the status indicator to indicatesuccess or failure of the internal memory verification operation duringa memory test operation, wherein the controller bypasses at least onememory sub-operation in order to perform the internal memoryverification operation.
 68. The system of claim 67, wherein the memorydevice further includes a comparator for comparing a sensed voltage of aselected memory cell to a reference voltage, wherein the controller setsthe status indicator as a function of the comparison.
 69. The system ofclaim 68, wherein the comparator compares the sensed voltage of theselected cell to a program reference voltage.
 70. The system of claim68, wherein the comparator compares the sensed voltage of the selectedcell to an erase reference voltage.
 71. The system of claim 67, whereinthe controller performs each of the plurality of memory operations byexecuting one or more memory sub-operations according to auser-configurable flow register.
 72. A system, comprising: a processor;and a memory device connected to the processor, comprising: an array ofmemory cells; a controller coupled to the array for performing aplurality of memory operations on the array of memory cells including aninternal memory verification operation; and an externally availablestatus indicator coupled to the controller, wherein the controller setsthe status indicator to indicate success or failure of the internalmemory verification operation, wherein the controller performs each ofthe plurality of memory operations by executing one or more memorysub-operations according to a user-configurable flow controller, andwherein the controller bypasses at least one of the memorysub-operations in order to perform the internal memory verificationoperation.
 73. The system of claim 72, wherein the controller bypassesthe memory sub-operations in response to a user configurable controlparameter stored in a data storage element of the memory system.
 74. Thesystem of claim 72, wherein the controller bypasses a memory erasesub-operation in order to perform a program-verify memory operation. 75.The system of claim 72, wherein the controller bypasses a memorypre-programming sub-operation in order to perform an erase-verify memoryoperation.
 76. A flash memory device comprising: a plurality ofnon-volatile memory cells; test mode circuitry to place the flash memorydevice in test mode a flow controller for causing the memory device tobypass at least one of a plurality of memory erase operations while inthe test mode; and an externally accessible status register comprising astatus register bit, the status register bit is programmable to indicatesuccess or failure of a test operation performed on the plurality ofnon-volatile memory cells, such that the status register bit can be readby a device external to the flash memory device.
 77. A flash memorydevice comprising: a plurality of non-volatile memory cells; and acontroller coupled to the array, wherein the controller performs each ofa plurality of memory operations on the plurality of non-volatile memorycells by executing one or more memory sub-operations according to aprogrammable flow controller; and wherein the flow controller causes thememory device to bypass at least one of the plurality of memoryoperations in a test mode.